TSMC Rejects ASML's $400M Chip Machines Through 2029, Citing Eye-Watering Costs

TSMC has flat-out refused to deploy ASML's bleeding-edge high-NA EUV lithography machines through 2029, telling investors the price tag is simply too brutal to justify. The Dutch equipment maker's latest systems cost up to €350-400 million each, more than triple traditional EUV tools, and TSMC's leadership isn't buying the math.

TSMC senior vice-president Kevin Zhang delivered the blunt assessment at a May 2024 Amsterdam technology symposium: "I like the high-NA EUV's capability, but I don't like the sticker price." The world's largest contract chipmaker has calculated that sticking with existing EUV machines and advanced packaging techniques delivers better economics than jumping to ASML's next generation.

The rejection hits ASML hard. These machines represent a decade of R&D and the company's primary growth driver through the decade. With TSMC representing roughly 35% of ASML's revenue, losing their biggest customer's immediate adoption threatens ASML's near-term financial projections.

Rather than pony up for ASML's high-NA systems, TSMC is betting on clever engineering workarounds. The company unveiled roadmap chips that achieve smaller, faster processors through aggressive use of existing EUV machines combined with advanced 3D packaging techniques. This approach layers multiple chips vertically, creating larger effective processors without requiring the most expensive lithography.

The strategy mirrors what Apple and NVIDIA already do, combine multiple smaller dies into one powerful package. TSMC's approach extends Moore's law by shrinking the spaces between transistors on existing 5nm and 3nm processes while stacking them vertically. It's less sexy than pure next-gen lithography but dramatically cheaper.

This pivot saves billions in capex while maintaining competitiveness. TSMC's foundry rivals like Samsung and Intel face the same calculation, potentially creating a collective freeze on high-NA adoption that could strand ASML with expensive inventory.

ASML hasn't taken the criticism lying down. CFO Roger Dassen pushed back in Dutch tech publication Bits and Chips, arguing high-NA EUV becomes "clearly the most cost-effective solution" when viewed over a decade-long production timeline. The company claims customers will eventually need these machines for sub-2nm processes regardless of current sticker shock.

The equipment maker points to breakthrough capabilities: high-NA systems can print features 1.7x smaller than current EUV, theoretically enabling chips with 2.8x more transistors. ASML executives frame the upfront cost against the total cost of ownership, suggesting customers who delay adoption will face higher per-wafer costs later.

Still, the company quietly acknowledges reality. ASML is reportedly delivering only a handful of high-NA systems this year, far below original projections, with Intel and Samsung taking early units while TSMC sits out. The reduced volume reflects broader industry hesitation about the technology's economics.

TSMC's decision creates a domino effect throughout the semiconductor supply chain. Equipment suppliers beyond ASML face delayed orders as foundries stretch current-generation tools. Memory makers like SK Hynix and Micron, who rely on TSMC's process leadership, must recalibrate their own roadmap investments.

The freeze particularly impacts companies betting on 2nm processes launching in 2026-2027. Apple, NVIDIA, and AMD, all TSMC customers, may need to adjust their product timelines or accept larger chip sizes. The delay could temporarily benefit Intel, which has committed to high-NA EUV for its 18A process, giving them a potential density advantage when TSMC competitors lag.

Chip design software companies like Synopsys and Cadence also face uncertainty. Their 2nm design tools assume high-NA availability, potentially forcing expensive recalibration if adoption stalls industry-wide.

TSMC's 2029 timeline isn't arbitrary, it aligns with when 2nm processes become cost-competitive for mainstream production. The company likely calculated that by 2029, high-NA machine costs will drop 30-40% through economies of scale and improved yields, making the economics finally pencil out.

This creates a high-stakes waiting game. If TSMC's packaging-centric approach delivers competitive performance, other foundries may follow suit, creating a multi-year lull in lithography upgrades. Conversely, if Intel or Samsung gain significant advantages using high-NA EUV earlier, TSMC could face pressure to accelerate adoption regardless of cost.

The broader implication: Moore's law increasingly depends on packaging innovation rather than pure lithography advances. This shifts power toward companies mastering advanced packaging, potentially benefiting TSMC's chip-on-wafer-on-substrate (CoWoS) technology while diminishing ASML's pricing power.